During the last years, different projects and initiatives addressed the main high-level research topics related to mixed criticality: certification by design, reconfiguration, fault detection, fault isolation and redundancy. However, some important challenges remain, being one of them the power consumption management and optimization in dependable mixed-criticality systems. Power is another resource (together with time and space) that has to be shared among different applications and the available energy has to be shared by all running applications in a mixed criticality system.
SAFEPOWER will advance the state-of-the-art towards a low-power reference architecture combining periodic time-triggered and event-triggered rate-constrained activities with power-efficient techniques-
The main objective of SAFEPOWER is to enable the development of cross-domain mixed-criticality systems with low power, safety and security requirements by means of the following key contributions:
The external assessment with respect to safety certification standards (e.g., IEC-61508) of the certifiable subset of the architecture and the power management techniques in order to pave the way towards the early adoption of the technology for the development of mixed criticality CRTES with safety requirements.
The definition and implementation of built-in security mechanisms that support the safety and low-power management of the system (e.g., authenticity, availability). These contributions will, for the first time until now, enable the use of low-power features in mixed critical embedded systems with no or at least controllable impact on safety and security features. This will enable the development of low power mixed criticality CRTES under the strict safety requirements imposed by current safety standards (e.g., IEC-61508).
Peio Onaindia and Tomaso Poggi and Mikel Azkarate-askatsua and Kim Grüttner and Maher Fakih and Salvador Peiro and Patricia Balbastre; Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29 – 31, 2018 ; 2018
Razi Seyyedi and Sören Schreiner and Maher Fakih and Kim Grüttner and Wolfgang Nebel; Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29 – 31, 2018; 2018
Irune Yarza and Mikel Azkarate-Askasua and Kim Grüttner and Wolfgang Nebel; 10th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO); 01 / 2018
Sören Schreiner and Razi Seyyedi and Maher Fakih and Kim Grüttner and Wolfgang Nebel; International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) XVIII, Samos Island, Greece, July 15-19, 2018; 07 / 2018
Maher Fakih and Sebastian Warsitz; HIP3ES 2017 ; 01 / 2017
Christof Schlaak and Maher Fakih and Ralf Stemmer; HIP3ES 2017; 01 / 2017
Maher Fakih, Alina Lenz, Mikel Azkarate-Askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser, Adele Maleki, Johnny Öberg, Mohamed Tagelsir Mohammadat, Jon Pérez-Cerrolaza, Ingo Sander, Ingemar Söderquist; Microprocessors and Microsystems; 0May / 2017
Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO); 01 / 2017
Ralf Stemmer and Maher Fakih; MBMV 2017; 02 / 2017
Razi Seyyedi, M. T. Mohammadat, Maher Fakih, Kim Grüttner, Johnny Öberg and Duncan Graham; 12th IEEE International Symposium on Industrial Embedded Systems (SIES); 06 / 2017
Ralph Görgen and Duncan Graham and Kim Grüttner and Larry Lapides and Sören Schreiner; 10 / 2016
Alina Lenz and Mikel Azkarate-Askasua Blázquez and Javier Coronel and Alfons Crespo and Simon Davidmann and Juan Carlos Diaz Garcia and Nera González Romero and Kim Grüttner and Roman Obermaisser and Johnny Öberg and Jon Perez and Ingo Sander and Ingemar Söderquist; Euromicro Conference on Digital System Design (DSD); 08 / 2016
Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; Integrating Dataflow, Embedded computing and Architecture (IDEA'2016); 04 / 2016