SafePower Safe and secure mixed-criticality systems with low power requirements (Leider nur in Englisch verfügbar.)


During the last years, different projects and initiatives addressed the main high-level research topics related to mixed criticality: certification by design, reconfiguration, fault detection, fault isolation and redundancy. However, some important challenges remain, being one of them the power consumption management and optimization in dependable mixed-criticality systems. Power is another resource (together with time and space) that has to be shared among different applications and the available energy has to be shared by all running applications in a mixed criticality system.

SAFEPOWER will advance the state-of-the-art towards a low-power reference architecture combining periodic time-triggered and event-triggered rate-constrained activities with power-efficient techniques-


The main objective of SAFEPOWER is to enable the development of cross-domain mixed-criticality systems with low power, safety and security requirements by means of the following key contributions:

  • The definition and development of a cross-domain mixed-criticality and low power reference architecture upon multicore/heterogeneous processors. The SAFEPOWER architecture will ensure the properties of power/energy/temperature awareness in combination with real-time support, time and space partitioning, reliability and security and provide the foundation for the development of applications (e.g., railway, aerospace), while abstracting from the details from the underlying implementation technologies.
  • The definition, implementation and demonstration of a set of mixed-criticality compliant low-power techniques and power management procedures that can be used in the development of mixed criticality Critical Real Time Embedded Systems (CRTES) mixed criticality CRTES with safety and security requirements.
  • The development of platforms and tools to enable and facilitate the development of low power mixed criticality CRTES, including software and hardware components:
    a. A Printed Circuit Board (PCB) implementation consisting of domain specific FPGAs/SoCs that can be plugged on a main board which enables the observability of power consumption and timing through dedicated measurement circuits
    b. A virtual platform environment for the early analysis, simulation, complexity-management and verification of potential low-power mixed criticality solutions.
    c. An Embedded Hypervisor to facilitate the integration and implementation of low power services (communication services, fault-tolerance services, low power load scheduling, diagnostic services) into mixed criticality systems.

The external assessment with respect to safety certification standards (e.g., IEC-61508) of the certifiable subset of the architecture and the power management techniques in order to pave the way towards the early adoption of the technology for the development of mixed criticality CRTES with safety requirements.

The definition and implementation of built-in security mechanisms that support the safety and low-power management of the system (e.g., authenticity, availability). These contributions will, for the first time until now, enable the use of low-power features in mixed critical embedded systems with no or at least controllable impact on safety and security features. This will enable the development of low power mixed criticality CRTES under the strict safety requirements imposed by current safety standards (e.g., IEC-61508).


Projektleitung Intern

Projektleitung Extern

Dr. Kim Grütthner
Automatic SDF-based Code Generation from Simulink Models for Embedded Software Development

Maher Fakih and Sebastian Warsitz; HIP3ES 2017 ; 01 / 2017

Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs

Christof Schlaak and Maher Fakih and Ralf Stemmer; HIP3ES 2017; 01 / 2017

SAFEPOWER project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Maher Fakih, Alina Lenz, Mikel Azkarate-Askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser, Adele Maleki, Johnny Öberg, Mohamed Tagelsir Mohammadat, Jon Pérez-Cerrolaza, Ingo Sander, Ingemar Söderquist; Microprocessors and Microsystems; 0May / 2017

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO); 01 / 2017

Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs

Razi Seyyedi, M. T. Mohammadat, Maher Fakih, Kim Grüttner, Johnny Öberg and Duncan Graham; 12th IEEE International Symposium on Industrial Embedded Systems (SIES); 06 / 2017

Integrating Power Models into Instruction Accurate Virtual Platforms for ARM-based MPSoCs

Ralph Görgen and Duncan Graham and Kim Grüttner and Larry Lapides and Sören Schreiner; 10 / 2016

SAFEPOWER project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Alina Lenz and Mikel Azkarate-Askasua Blázquez and Javier Coronel and Alfons Crespo and Simon Davidmann and Juan Carlos Diaz Garcia and Nera González Romero and Kim Grüttner and Roman Obermaisser and Johnny Öberg and Jon Perez and Ingo Sander and Ingemar Söderquist; Euromicro Conference on Digital System Design (DSD); 08 / 2016

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; Integrating Dataflow, Embedded computing and Architecture (IDEA'2016); 04 / 2016

CAF Signalling, S.L.
fent Innovative Software Solutions
Imperas Software Ltd.
Kungliga Tekniska Högskolan (Royal Institute of Technology)
Universität Siegen


Start: 01.01.2016
Ende: 31.12.2018

Website des Projekts



GA: 687902