Helms, Domenik and Meyer, Olaf and Hoyer, Marco and Nebel, Wolfgang
Intl. Symposium on Low Power Electronic Design
Using our framework supporting simultaneous behavioral to RTL synthesis, component-wise floorplanning, as well as ABB (adaptive body biasing) and VDD aware power and delay prediction, we present a performance neutral methodology for optimal VDD-island generation and multiple ABB application. We show that tuning supply and body voltage for the entire design reduces the total energy dissipation by 4.6-38.1% without any performance loss. By allowing more than one body voltage and without optimizing the floorplan, the savings do not rise any further. Carefully floorplanning the design, we can additionally use VDD-islands reducing the power by 8.7- 49.2%. In addition to the power savings, the power and delay variability due to PTV variation can be reduced with all proposed ABB approaches, if we assume that only the chip structure has to be fixed at design time, but the voltage levels can be adapted after the system manufacturing.
01 / 2007
MAP2 Micro-Architectural Power Management: Methoden, Algorithmen und prototypische Werkzeuge CLEAN Controlling LEAkage power in NanoCMOS SoCs