Trace-Based Power State Machine Modelling

Daniel Lorenz and Vincent Ortland and Kim Grüttner
Forum on specification & Design Languages (FDL) 2014
Due to the increasing algorithmic complexity oftodays embedded systems, the consideration of extra-functional properties becomes even more important. Extra-functional properties such as timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gatelevel, several techniques are available, but there is still a lack of methods and tools for power estimation and analysis at electronic system level (ESL) and above. In todays systems most of the hardware is not design from scratch, but bought as black-box components from IP vendors. Our Power State Machine (PSM) model enables power simulation of these components at ESLby deriving the power of communication at the component’s interfaces. In this work we present an Eclipse plug-in which supports the designer or user of a black-box IP component in creating the PSM model based on gate-level simulations and power estimations.
10 / 2014
Methodik zum Entwurf von energiesparenden, verifizierten Systemen