Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim
Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013
The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model- checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.
03 / 2013
European Design and Automation Association
DATE '13
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