Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg
1st International Workshop on Investigating Dataflow in Embedded computing Architecture (IDEA)
The timing predictability of multi-core platforms with hard real-time applications is much more challenging than that of traditional platforms due to their large number of shared processing, communication and memory resources. Yet, this is an indispensable challenge for guaranteeing their safe usage in safety critical domains (avionics, automotive).
In this paper, a real-time analysis based on model-checking is proposed. The model-checking based method allows to guarantee timing bounds of multiple Synchronous Data Flow Application (SDFA) implementations. This approach utilizes Timed Automata (TA) as a common semantic model to represent WCET of software components (SDF actors) and shared communication resource access protocols for buses, DMA, private local and shared memories of the multi-core platform. The resulting network of TA is analyzed using the UPPAAL model-checker for providing safe timing bounds of the implementation.
We demonstrate our approach using several image processing algorithms and a multi-phase electric motor control algorithm mapped to Infineon's TriCore-based Aurix multi-core hardware platform with two different inter-core communication styles: burst- and single-beat transfer. Our approach shows a significant precision improvement compared with the worst-case bound
calculation based on analytical upper-bound delays for every shared resource access.
1 / 2015
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