This report presents the results of an analysis on state-of-the-art leakage estimation. The research focused to approaches at the register transfer level, but also important contribution concerning lower level estimation was regarded. This report is organized as follows: After a short introduction, in section 2, the physical sources of leakage are analyzed and the different types of leakage are detailed in order to help readers who are not familiar with leakage itself to better understand the basics of leakage. Section 3 details, which effects impact the amount of leakage current on a chip. Readers, who are familiar with dynamic power estimation will see, that the scope of effects differs significantly from that used for dynamic power estimation. The focus in leakage estimation is more a modeling of physical and process dominated parameters - not a data dependent macro-modeling. A general review on low level optimization techniques addressing leakage is presented in section 4. Different existing methodologies of estimating different impacts affecting leakage are presented in section 5. A suggestion on how the published results could be used for a high-level leakage estimation is presented in section 6 the data acquisition and patents related to presented approaches are discussed in sections 7 and 8. In the end, section 9 concludes this report.