Schwarz, A. and Mertsching, B. and Brucke, Matthias and Nebel, Wolfgang and Hansen, M. and Kollmeier, B.
A digital VLSI implementation of an algorithm modeling the effective signal processing of the human auditory system is presented. The model consists of several stages psychoacoustically and physiologically motivated by the signal processing in the human ear and was successfully applied to various speech processing applications. The processing scheme was partitioned for implementation in a chipset of three ASICs. The area of each chip is about 70 mm 2 in a 0.7 Âµm technology. It is demonstrated how an application of the model has been used to determine the necessary wordlengths for a transfer of the floating point algorithm into a version suitable for a hardware implementation. The developed synthesizable VHDL-descriptions of this fix point version are now evaluated in real time on FPGAs and will be manufactured as ASICs in a later version.