Schmidt, Eike and Huijbrechts, E. and Seelen, E. and Nieuweboer, W. and Kruse, Lars and von Cölln (Jochens), Gerd and Nebel, Wolfgang
This paper addresses the problem of modeling the power consumption of on-chip ROMs for gate-level and RT-level power estimations. A route to memory power model development is presented that is also applicable to other memory architec-tures. The model proposed operates within an error margin of less than 5%.
01 / 1998
PATMOS 1998, Lyngby / Denmark
Power Estimation for fast Exploration of Embedded Systems