To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. ABB and AVS.
Lecture Notes in Computer Science (LNCS, volume 4644)