Lower and upper bounds on the switching activity in scheduled data flow graphs

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Nebel, Wolfgang
In this paper we present an approach to calculate lower and upper bounds for the switching activity in scheduled data flow graphs. The technique can be used to prune the design space in high level synthesis for low power before allocation and binding of functional units and registers. The low power allocation and binding problem is formu-lated. It is shown that this problem can be relaxed to the bipartite weighted matching problem which is solvable in O(n3) where n is the number of functional units or registers
01 / 1999
ISLPED 1999, International Symposium on Low Power Electronics and Design, San Diego, Californien, 1999
Power Estimation for fast Exploration of Embedded Systems

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