1st International Workshop on Investigating Dataflow in Embedded Computing Architecture (IDEA 2018)
Predicting the performance of parallel programs for large-scale parallel platforms is difficult due to the disparity between development system and target platform. Additionally, energy efficiency is becoming a universal concern, and platforms move towards highly heterogeneous systems containing GPUs, FPGAs, and other unconventional processing elements.In this paper we propose a static macro data-flow mapping and scheduling tool that is able to handle large parallel applications targeting heterogeneous platforms. It optimizes overall run time and energy consumption at the same time with a user-configurable cost function, allowing a selectable trade-off between both properties.
01 / 2015
FiPS Developing Hardware and Design Methodologies for Heterogeneous Low Power Field Programmable Servers