Considering Variation and Aging in a Full Chip Design Methodology at System Level

BIB
Domenik Helms and Kim Grüttner and Reef Eilers and Malte Metzdorf and Kai Hylla and Frank Poppen and Wolfgang Nebel
Proceedings of The 2014 Electronic System Level Synthesis Conference (ESLsyn'14), May 31- Jun 01 2014, San Francisco, CA, USA
We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level backannotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multiphysics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
5 / 2014
inproceedings
ECSI
RELY
Design for RELIABILITY of SoCs for Applications like Transportation, Medical, and Industrial Automation
Contrex
Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties