An ESL Timing & Power Estimation and Simulation Framework for Heterogeneous SoCs

BIB
Kim Grüttner and Philipp A. Hartmann and Tiemo Fandrey and Kai Hylla and Daniel Lorenz and Stefan Stattelmann and Björn Sander and Oliver Bringmann and Wolfgang Nebel and Wolfgang Rosenstiel
Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Samos, Greece, July 14-17, 2014
Consideration of an embedded system’s timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from a functional C/C ++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios.
7 / 2014
inproceedings
COMPLEX
COdesign and power Management in PLatform-based design space EXploration
Contrex
Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties