Algorithmic level low power optimisations for power reduction in hearing aids

Sarker, Bodhisatya and Nebel, Wolfgang and Frimont, Sven
With the ever increasing functionalities on chip, the issue of power consumption becomes more and more critical. In order to investigate into the potential of reducing power by means of design techniques, analysis of power dissipation has to be made. There are many stages in the design, like System level, RT level etc. These various stages of design offer various degrees of freedom and opportunities for reduction in power[1].The highest percentage of power reduction gains are offered at the system and algorithmic level, both in terms of time and effort. Hence, we concentrated at the system level for investigating into the various reduction opportunities. For this investigation, we choose the Overlap-Add Algorithm, a common Algorithm used in hearing aids.
01 / 2003
Work in Progress Session in Verbindung mit dem EUROMICRO Symposium on Digital System Design DSD 2003

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