Latency Optimization for a Reconfigurable, Self-Timed and Bit-Serial Architecture

BIB
Dittmann, Florian and Rettberg, Achim and Weber, Raphael
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms
This paper presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was recently patented and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This paper focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization.
06 / 2007
1-60132-026-4
inproceedings
CSREA Press
152
Toomas P. Plaks

OFFIS Autoren

Jun.-Prof. Dr. Achim Rettberg
Jun.-Prof. Dr.
Achim Rettberg