In order to increase the maximum economic sizes of Field-Programmable Gate Arrays (FPGAs) through increasing the yield, there are basically two different strategies. First it is possible to add redundancy, i.e. spare cells and selector circuits. This solution has been successfully applied to large memories and to simple FPGA-architectures. Second, it is possible to generate specific placements for each partially defective FPGA. Using this method for a mass-produced product is not feasible, because of the time cost of remapping the design for each FPGA. In the new approach I am proposing, hard macros are used to represent pre-placed and pre-routed sub-circuits. The main idea is to use timing information of the paths in a design to replace selected macros in these paths with a defect tolerant version. The approach consists of three steps, only the third one being repeated for each defective FPGA: 1. Generation of a hard macro library 2. Generation of an adaptable bitstream for the configuration of partially defective FPGAs 3. The adjustment of the bitstream for each FPGA within a mass-production.