SoC designers face two main problems nowadays. First, the complexity of ASICs is doubling every 18 months, following Moore s Law, while the productivity of designers evolves at a much slower pace. This leads to a problem known as the design gap . Second, designers of sub-micron devices have to observe the power dissipation of their SoC. The enhancement of battery energy capacity fails to keep up with increasingly power consuming applications. This is critical to handheld products like cellular telephones and PDAs, which will drive the market in a future world of wireless communication. Higher levels of abstraction need to be introduced to approach the design gap and in order to handle the billions of transistors of future designs. Synopsys offers its Behavioral Compiler (BC), which introduces this higher level of abstraction. Designers do not need to schedule manually and do binding of operations if they enter the algorithms only. Integrating BC into a design flow together with Synopsys PowerCompiler offers the opportunity of a high-level low-power design-flow with automated gated clock insertion and operand isolation. This results in a promising methodology reducing development time and power dissipation. This paper introduces a behavioral level low power design flow and evaluates its applicability based on a design case. The design space is being explored and several architectures for the chosen filter algorithms are synthesized starting from a behavioral HDL specification of a bank of infinite impulse response filters (IIR). Each solution is examined at gate level for power dissipation.
01 / 2001
SNUG Boston 2001: 3th Annual Synopsys User Group Conference, Sept. 10.-12. 2001, Newton, Massachusetts
PEOPLE Power Estimation for fast Exploration of Embedded Systems POET Verlustleistungs-Optimierungen eingebetteter Systeme