CLEAN Controlling LEAkage power in NanoCMOS SoCs


Power consumption of electronic devices nowadays is a major challenge when developing embedded sytems, that is integrated circuits. Continually shrinking feature sizes of micro-electronic systems, now reaching nano-scale, led to a dramatic increase in static power (leakage power). Mastering the resulting high power consumption and unreliable device behaviour will be the objective of the European funded integrated project (IP) CLEAN.

In CLEAN new methods and tools for designing chips will be reasearched and developed, aiming at high power savings during runtime of the later electronic products. Besides an improved battery duration, taking leakage power into account will prevent unnecessary re-designs, thus reducing costs directly affecting time to market.

With CLEAN OFFIS expands its competence gained from previous projects PEOPLE, POET and LEMOS in the field of analysis and optimization of embedded systems. At the same time OFFIS is the technical coordinator of the consortium, including well-known European research institutes and companies, like Infineon and ST-Microelectronics, accompanied by several SMEs, like the successful OFFIS-spin-off ChipVision Design Systems AG, which drives the commercial development and distribution of the tools arising from OFFIS.


Scientific Director

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

Helms, Domenik and Nebel, Wolfgang; Proceedings on the 14th IEEE Internactional Conference on Electronics, Circuits, and Systems; 12 / 2007

System Level Optimization of Static Power Consumption in Nano-CMOS Circuits

Helms, Domenik; Proceedings of the 14th International Conference MIXDES 2007; 001 / 2007

Voltage- and ABB_Island Optimization in High Level Synthesis

Helms, Domenik and Meyer, Olaf and Hoyer, Marco and Nebel, Wolfgang; Intl. Symposium on Low Power Electronic Design; 001 / 2007

Modelling the impact of high level leakage optimization techniques on the delay of RT-components

Hoyer, M. and Helms, D. and Nebel, W.; Proceedings of the PATMOS 2007; 001 / 2007

Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation

Helms, Domenik and Ehmen, Günter and Nebel, Wolfgang; Tagungsband; 10 / 2006

Leakage Currents in Nanometer CMOS

Nebel, Wolfgang and Helms, Domenik and Keshavarzi, Ali; -; 10 / 2006

Leakage Power Modeling, Estimation and Optimization

Helms, Domenik; Tagungsband für die Workshopteilnehmer; 004 / 2005

Leakage in CMOS Circuits - An Introduction

Helms Domenik and Schmidt, Eike and Nebel, Wolfgang; Tagungsband; 009 / 2004

Power Management Aware Low Leakage Behavioural Synthesis

Rosinger, S. and Schröder, K. and Nebel, W.; Proceedings of the 12th Euromicro Conference on Digital System Design; 001 / 2009

RT Level Makro Modelling of Leakage and Delay under Realistic PTV Variation

Helms, Domenik and Hoyer, Marko and Rosinger, Sven and Nebel, Wolfgang; Proceedings of LPonTR; 005 / 2008

Leakage models for high level power estimation

Domenik Helms ; Reef Eilers ; Malte Metzdorf ; Wolfgang Nebel; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 11 / 2017

Budapest University of Technology and Economics
BullDAST s.r.l.
ChipVision Design Systems AG
Commissariat à l’Energie Atomique LETI Laboratory
Consorzio per la Ricerca e l’Educazione Permanente
Edacentrum GmbH
Infineon Technologies AG
Politechnika Warszawska
Politecnico di Torino
STMicroelectronics srl
DTU - Danmarks Tekniske Universitet
Universitat Politecnica de Catalunya


Start: 31.10.2005
End: 30.10.2008

Related projects


Micro-Architectural Power Management: Methods, Algorithms and Prototype tools


Power Estimation of Embedded Systems


Power Optimization of Embedded systems