POET Power Optimization of Embedded systems


The main objective of the POET project is to develop a new designmethodology and tool suite for power estimation and optimisation in heterogeneous embedded SoC designs. The key innovation of the approach is to enable design space exploration for low power system architectures, algorithm optimisations and system partitioning - from the earliest design steps seamlessly through to RT level (i.e. to the interface with standard industrial synthesis tools). The POET design framework will operate at each level of abstraction, i.e. algorithmic, hardware/software partition, cycle-accurate RT level. POET tools will manage and optimise all major contributors to power dissipation in large SoC designs such as ASICs, cores and processors, memories, communication and I/O interfaces.

The main result of the project developed by OFFIS in co-operation with theUniversity of Oldenburg is an enhancement of the ORINOCO tool suite. New optimization features at the source level and support for low power high-level synthesis will be integrated.


Power Estimation at all Levels of Abstraction

Nebel, Wolfgang and Papaefthymio, Marios; 001 / 2005

Interconnect Driven Low Power High-Level Synthesis

Stammermann, Ansgar and Helms, Domenik and Schulte, Milan and Schulz, Arne and Nebel, Wolfgang; Tagungsband PATMOS 2003; 001 / 2003

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Stammermann, Ansgar; Tagungsband ICCAD; 001 / 2003

Memory power optimisation in an application specific algorithm

Sarker, Bodhisatya and Schulte, Milan and Hillers, Mark and Nebel, Wolfgang; Tagungsband; 005 / 2003

Low Power Optimisation techniques in Overlapp Add algorithm

Sarker, Bodhisatya and Nebel, Wolfgang and Schulte, Milan; Tagungsband (CCCT'03); 008 / 2003

System-Level Power Optimization

Nebel, Wolfgang; Tagungsband, DSD 2004, Rennes / France; 009 / 2004

High-Level Power Estimation and Analysis

Nebel, Wolfgang and Helms, Domenik; Low-Power Electronics Design; 001 / 2005

Low Power Design for SoCs

Nebel, Wolfgang and Helms, Domenik and Schmidt, Eike and Schulte, Milan and Stammermann, Ansgar; Tagungsband; 10 / 2002

An Improved Power Macro-Model for Arithmetic Datapath Components

Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel; PATMOS; 09 / 2002

Memory Power Models For Multilevel Power Estimation And Optimization

Schmidt, Eike and von Cölln (Jochens), Gerd and Kruse, Lars and Theeuwen, Frans and Nebel, Wolfgang; 001 / 2002

Automatic Nonlinear Memory Power Modelling

Schmidt, Eike and von Cölln (Jochens), Gerd and Kruse, Lars and Theeuwen, Frans; 001 / 2001

ORINOCO: Verlustleistungsanalyse und Optimierung auf der algorithmischen Abstraktionsebene

Stammermann, Ansgar and Kruse, Lars and Schmidt, Eike and Pratsch, Alexander and Schulte, Milan and Schulz, Arne and Nebel, Wolfgang; 001 / 2001

System Level Optimization and Design Space Exploration for Low Power

Stammermann, Ansgar and Kruse, Lars and Nebel, Wolfgang and Pratsch, Alexander and Schmidt, Eike and Schulte, Milan and Schulz, Arne; 001 / 2001

Comparison of a RT - and Behavioral-Level Design Entry Regarding Power

Nebel, Wolfgang and Poppen, Frank; 001 / 2001

Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Stammermann, Ansgar and Schulz, Arne and Macii, E. and Nebel, Wolfgang; 001 / 2001

Power Modeling of Embedded Memories

Schmidt, Eike; 001 / 2003

Micro-Architecture-Level Power Analysis and Optimazion

Nebel, Wolfgang and Schmidt, Eike; Tagungsband; 001 / 2004

Alcatel SEL
ARM Limited
Atmel Corporation
BullDAST s.r.l.
CEFRIEL Società consortile a Responsabilità Limitata
ChipVision Design Systems AG
Politecnico di Torino


Start: 31.08.2001
End: 27.02.2005

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