PEOPLE Power Estimation of Embedded Systems

Goal

The objective of the PEOPLE project is the development of a tool-suiteof power estimators for embedded systems which enables a design flow for fast, yet accurate power estimation and optimization of designs starting at the behavioural level of abstraction downto the register transfer level. The target architecture of the systems to be designed using this design flow may contain hard and soft macros, RAMs, ROMs, and complex IP cores like processors. The tool-suite consists of power estimators for the software part, the behavioural level and RT-level as well as for memories.

 

OFFIS contribution to the project are the behavioural level and thememory power estimators. The behavioural power estimator aims at the analysis of complex hardware modules at the behavioural level of abstraction described in VHDL. The power estimation of complex hardware modules at this level before high-level synthesis is needed to explore different hardware/software partitionings, to compare the power dissipation of a custom cell against an IP cell, and to evaluate different target technologies. The power estimation process will be simulation based using any commercial VHDL simulator. The data statistics are extracted by profiling the VHDL description while the circuit structure is estimated from transformations of a control data flow graph without synthesising an RT level netlist. The power estimator will rely on a characterized RT module library. The memory power estimator is also characterization based. It will consider off-chip as well as on-chip memories. The memory power estimator will not be a stand-alone tool but integrated into the behavioural power estimator.

 

The project is funded by the Commission of the European Union. The projectpartners are the CAD tool development company Synopsys LEDA, Italtel and Alcatel as tool users, ARM doing the microprocessor characterization for software power estimation, and the Politecnico di Torino, a research institute focussing on RTL and software power estimation.

Persons
Publications
Power Modeling of Embedded Memories

Schmidt, Eike; 001 / 2003

Low Power Design for SoCs

Nebel, Wolfgang and Helms, Domenik and Schmidt, Eike and Schulte, Milan and Stammermann, Ansgar; Tagungsband; 10 / 2002

Memory Power Models For Multilevel Power Estimation And Optimization

Schmidt, Eike and von Cölln (Jochens), Gerd and Kruse, Lars and Theeuwen, Frans and Nebel, Wolfgang; 001 / 2002

Automatic Generation of Complexity Functions for High Level Power Analysis

Schmidt, Eike and Schulz, Arne and Kruse, Lars and von Cölln (Jochens), Gerd and Nebel, Wolfgang; 001 / 2001

Automatic Nonlinear Memory Power Modelling

Schmidt, Eike and von Cölln (Jochens), Gerd and Kruse, Lars and Theeuwen, Frans; 001 / 2001

Comparison of a RT - and Behavioral-Level Design Entry Regarding Power

Nebel, Wolfgang and Poppen, Frank; 001 / 2001

Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Stammermann, Ansgar and Schulz, Arne and Macii, E. and Nebel, Wolfgang; 001 / 2001

ORINOCO: Verlustleistungsanalyse und Optimierung auf der algorithmischen Abstraktionsebene

Stammermann, Ansgar and Kruse, Lars and Schmidt, Eike and Pratsch, Alexander and Schulte, Milan and Schulz, Arne and Nebel, Wolfgang; 001 / 2001

System Level Optimization and Design Space Exploration for Low Power

Stammermann, Ansgar and Kruse, Lars and Nebel, Wolfgang and Pratsch, Alexander and Schmidt, Eike and Schulte, Milan and Schulz, Arne; 001 / 2001

Lower bounds on the power consumption in scheduled data flow graphs with resource constraints

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Stammermann, Ansgar and Nebel, Wolfgang; 001 / 2000

Array-Datenfluß-Analyse am Abhängigkeitsgraphen

Kopperschmidt, Klaus; 10 / 1999

Low power binding heuristics

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Nebel, Wolfgang and Stammermann, Ansgar; 001 / 1999

Lower and upper bounds on the switching activity in scheduled data flow graphs

Kruse, Lars and Schmidt, Eike and von Cölln (Jochens), Gerd and Nebel, Wolfgang; 001 / 1999

Power consumption of on-chips roms: Analysis and modeling.

Schmidt, Eike and Huijbrechts, E. and Seelen, E. and Nieuweboer, W. and Kruse, Lars and von Cölln (Jochens), Gerd and Nebel, Wolfgang; 001 / 1998

Partners
Alcatel SEL
ARM Limited
www.arm.com
Italtel
www.italtel.it
LEDA S.A.
Politecnico di Torino
www.polito.it
Siemens ICN S.p.A.

Duration

Start: 31.03.2000
End: 29.06.2001

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