The objective of the PEOPLE project is the development of a tool-suiteof power estimators for embedded systems which enables a design flow for fast, yet accurate power estimation and optimization of designs starting at the behavioural level of abstraction downto the register transfer level. The target architecture of the systems to be designed using this design flow may contain hard and soft macros, RAMs, ROMs, and complex IP cores like processors. The tool-suite consists of power estimators for the software part, the behavioural level and RT-level as well as for memories.

OFFIS contribution to the project are the behavioural level and thememory power estimators. The behavioural power estimator aims at the analysis of complex hardware modules at the behavioural level of abstraction described in VHDL. The power estimation of complex hardware modules at this level before high-level synthesis is needed to explore different hardware/software partitionings, to compare the power dissipation of a custom cell against an IP cell, and to evaluate different target technologies. The power estimation process will be simulation based using any commercial VHDL simulator. The data statistics are extracted by profiling the VHDL description while the circuit structure is estimated from transformations of a control data flow graph without synthesising an RT level netlist. The power estimator will rely on a characterized RT module library. The memory power estimator is also characterization based. It will consider off-chip as well as on-chip memories. The memory power estimator will not be a stand-alone tool but integrated into the behavioural power estimator.

The project is funded by the Commission of the European Union. The projectpartners are the CAD tool development company Synopsys LEDA, Italtel and Alcatel as tool users, ARM doing the microprocessor characterization for software power estimation, and the Politecnico di Torino, a research institute focussing on RTL and software power estimation.