RT Level Makro Modelling of Leakage and Delay under Realistic PTV Variation

BIB
Helms, Domenik and Hoyer, Marko and Rosinger, Sven and Nebel, Wolfgang
Proceedings of LPonTR
We present a modelling concept, accurately predicting the correlated leakage-delay distribution of entire RT components. The model regards all relevant parameters, known to either influence delay or leakage. Process variations enter the model in two ways: As totally uncorrelated parameter noise and totally correlated global variation by regarding the distribution of the per-component parameter mean. The influence of a correlation between process parameters on delay and leakage is also regarded. Additionally, several run-time dynamic parameters as temperature, supply voltage, well potential, and component state enter the model. The model consists of 3 modules, a PTV aware leakage model [1], and a PTV aware delay model [2], and additionally, a variation engine, fulfilling several purposes: combination of the delay and leakage models to describe the correct leakage-delay correlation, characterization of the correlation between process parameters, and translation of process variations into abstract binning classes for later use in high level estimation and synthesis tools. The modelling concept was developed for datapath RT components. Nevertheless, it can also describe full custom gate lists as a hard-macro1 and components with sequential logic with a slightly reduced accuracy in terms of leakage. The delay of sequential circuits can only be determined if their critical paths can be unrolled by our delay models. The main limitation of this approach is parameter gradients. Both sub-models for delay and leakage exploit the fact, that all model parameters are either constant (e.g. temperature or global parameter variation) or completely uncorrelated (statistic variations) for all parts of one component.
05 / 2008
inproceedings
33-34
CLEAN
Controlling LEAkage power in NanoCMOS SoCs
2008