Leakage Models for High Level Power Estimation

Helms, Domenik
The thesis presents a leakage estimation framework for RT components computing the dominant sources of leakage in sub-100nm CMOS devices, subthreshold leakage, gate tunnelling and pn-junction leakage. By regarding the most significant parameters temperature, supply voltage, and body voltage, as well as statistical and deterministic variation of the channel length, the oxide thickness and the channel doping concentration [1], the resulting model accuracy of 5% standard deviation against statistical SPICE-BSIM4 simulations is very high in consideration of the abstraction level.
03 / 2008
inproceedings
CLEAN
Controlling LEAkage power in NanoCMOS SoCs