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  1. Home
  2. Research
  3. Embedded System Design (ESD)

Embedded System Design (ESD)

Smaller, faster, more intelligent - but how secure?

Today, many products have integrated electronics. In a modern midsize car alone, numerous electronic systems are used to optimize comfort, safety and effi ciency. In the traffi c and transportation segment, this type of hard- and software system is also incorporated into traffic infrastructures; safety systems; and the coordination of transportation and materials fl ows in logistics. In the health sector embedded electronic systems have become indispensable, improving quality of life and off ering a range of options to maintain and regain health. Examples of such medically relevant solutions include hearing aids, pacemakers, mobile ECG or »lab-on-chip« devices that improve diagnosis and treatment options.

Some of these products have only become possible thanks to rapid developments in manufacturing technology that have allowed embedded hardware and software systems (HW/SW) to be produced in ever smaller, more compact forms. This  results in a continuous stream of new challenges for industry and research institutions. Ever smaller products must be incorporated into ever more complex system architectures that must simultaneously meet the increasing  requirements of modern applications regarding processing speed and energy efficiency. In addition to  this, globalized markets mean growing time pressure for development work and shorter product cycles. Developers are also faced with high cost pressures, since competition among mass-market products is fierce and margins are low. The smallest diff erences in price are often key competitive advantages. Many applications have the further complicating factor that the embedded HW/SW systems are often deployed in security-critical applications.

Various research groups at OFFIS and Oldenburg University have been investigating these issues and challenges for many years now. Their goals include modeling; analysis; and optimization at all design levels plus the automated synthesis of embedded HW/SW systems regarding performance, energy consumption, manufacturing fluctuations, ageing effects, environmental influences, required chip area, and, finally, costs. Further focuses are the development of suitable specification, verification, and synthesis methods for component-based design processes as well as formal analysis methods to ensure implementation requirements.

This work will be transferred to the Embedded System Design competence cluster to facilitate its bundling and research within a larger context. This will facilitate the development of methods, tools, and standards that assist the effi cient, secure development of microelectronic embedded systems in industrial design processes.

  • Applied Artificial Intelligence (AAI)
  • Architecture Frameworks (AF)
  • Cyber-Resilient Architectures and Security (CRAS)
  • Embedded System Design (ESD)
  • Human Machine Cooperation (HMC)
  • Multi-Scale Multi-Rate Simulation (MS²)
  • Sustainability
  • Safety Relevant Cyber Physical Systems (SRCPS)

Chairman of the Competence Cluster

Wolfgang Nebel
Wolfgang Nebel

Persons

B

Felix Böseler

E-Mail: felix.boeseler(at)offis.de, Phone: +49 441 9722-758

D

Werner Damm

E-Mail: werner.damm(at)uni-oldenburg.de

F

Martin Fränzle

E-Mail: Martin.Fraenzle(at)uni-oldenburg.de, Phone: +49 441 9722-500, Room: D122

K

Patrick Knocke

E-Mail: Patrick.Knocke(at)offis.de, Phone: +49 441 9722-402, Room: O91

Finn König

E-Mail: finn.koenig(at)offis.de, Phone: +49 441 9722-209

M

Mahsa Moazez

E-Mail: mahsa.moazez(at)offis.de, Phone: +49 441 9722-552, Room: Flx-P

N

Wolfgang Nebel

E-Mail: wolfgang.nebel(at)offis.de

W

Dr.-Ing. Jörg Walter

E-Mail: Joerg.Walter(at)offis.de, Phone: +49 441 9722-729, Room: O86

Projects

2023

ISOLDE

Customizable Instruction Sets and Open Leveraged Designs of Embedded riscv processors

Duration: 2023 - 2026

2021

KI embedded

KI-Grundlagenentwicklung für Embedded-Systems mit Leitanwendungen in Virtueller Sensorik und Brennstoffzellenregelung

Duration: 2021 - 2024

VE-VIDES

Duration: 2021 - 2024

2019

LUTNet

An energy-efficient AI network of elementary lookup tables

Duration: 2019 - 2020

ZL Produktion

Future Laboratory Manufacturing

Duration: 2019 - 2024

PANORAMA

Boosting Design Efficiency for Heterogeneous³ Systems

Duration: 2019 - 2022

2017

SAFE4I

Sicherer Automatischer Software-Entwurf für Industrieanlagen

Duration: 2017 - 2021

Productive4.0

Electronics and ICT as enabler for digital industry and optimized supply chain management covering the entire product lifecycle

Duration: 2017 - 2020

Digitaler Knoten 4.0

Duration: 2017 - 2019

2016

M2DC

Modular Microserver DataCentre

Duration: 2016 - 2019

EN: Alle Projekte aus dem Competence Cluster Embedded System Design (ESD)

Publications

2026

Modeling service choreographies and collaborations for autonomous mixed-fleet systems: using BPMN, IEC 61499, and SysML

Bianca Wiesmayr, Alois Zoitl, Jörg Walter, David Hästbacka ; Innovations in Systems and Software Engineering; 06 / 2026

URL DOI BIB
Physics-Guided Digital Twin for Power-Based Anomaly Detection in Industrial Robots

Muhammad Uddin, Jörg Walter, Michele Lora, Davide Cannizzaro, Davide Maria Gatta, Franco Fummi; IECON26; 2026

BIB
Runtime Monitoring for Safe Autonomous Mobile Robots: Special Session Paper

Mehlhop, Sven and Oppenheimer, Frank; 2026 Forum on Specification & Design Languages (FDL); 2026

DOI BIB

2025

A Formal Model Transformation from Data Flow Models to IEC 61499 Models

Malte Grave, Markus Meingast, Verena Klös, Alois Zoitl, Lisa Sonnleithner, Jörg Walter; IEEE 30th International Conference on Emerging Technologies and Factory Automation (ETFA); 09 / 2025

BIB
Aufrüsten der Prozessüberwachung im Druckguss, Teil 1 von 4

Slava Pachandrin, Jörg Walter, Julian Bargfrede, Norbert Hoffmann, Klaus Dilger; GIESSEREI - Fachzeitschrift für Technik, Innovation und Management; 01 / 2025

BIB
Contract-based design for robust networked control systems in industrial automation

Friederike Bruns, Jörg Walter, Andreas Rauh; ISA transactions; 09 / 2025

BIB
Enabling Manual-Controllable Compilation for Dataflow CGRAs

Felix Böseler, Jörg Walter, Verena Klös; IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW); 06 / 2025

BIB
Trust is Good, Monitoring is Better: FPGA-& TEE-Based Monitoring for Malware Detection

Friederike Bruns, Glaser Glaser, Florian Kogler, Jonas Lienke, Nithin Ravani Nanjundaswamy, Gregor Nitsche, Behnam R Perjikolaei, Jörg Walter; 13th IMA International Conference on Modelling in Industrial Maintenance and Reliability MIMAR; 2025

BIB
Validating the Design of CPS: Interfacing Simulations of Multi-Physics Components and Software with Contract-Based Monitoring

Friederike Bruns, Francesco Tosoni, Sven Mehlhop, Andreas Rauh, Sara Vinco, Jörg Walter, Frank Oppenheimer, Franco Fummi; 29th International Conference on Methods and Models in Automation and Robotics (MMAR); 08 / 2025

BIB

2024

A Rate-Parametric Dataflow Language for a Manual Controllable CGRA Compilation Flow

Böseler, Felix and Walter, Jörg; Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2024; 02 / 2024

BIB
EN: Alle Publikationen aus dem Competence Cluster Embedded System Design (ESD)
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