While feature sizes are continuously scaled towards atomic dimensions, industry is increasingly confronted with unexpected physical artefacts to be considered at each new technology node. Among these, process variation and parameter degradation lead to reliability concerns impacting integrated circuit design at all abstraction levels. As variation and degradation may become a limiting factor for future scaled technologies, there has been a tremendous research effort in understanding these artefacts. Versatile tools, allowing consideration of these artefacts and their combined impact during the design of ICs are still in their infancy.
Rather than developing yet another design support methodology, we aim to combine and refine existing reliability and variability prediction methodologies at the abstraction layers with highest industrial importance: Register transfer (RT) level - usual design entry, gate level – where most design for reliability (DfR) techniques are applied, and transistor level - where final sign-off is made.
MoRV will cover the strong relationship between variability and ageing, which are usually treated separately, fostering the idea of treating ageing as a form of time-dependent variability. Combined models from transistor, over gate, to RT level will be characterized directly from silicon measurement and all models will be able to interpret the same characterization data base from the silicon measurement.
MoRV is funded in the 7th Framework ICT of the European Union (Projectnumber 619234).
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