HW. Karner, C. Kernstock, Z. Stanojevi´c, O. Baumgartner, F. Schanovsky, M. Karner, D. Helms, R. Eilers, M. Metzdorf
Proceedings of the 2017 Intl. Symp. on VLSI Technology, Systems and Application
We present a novel approach for extracting the power-performance-area PPA parameter and their variability directly from a TCAD model of a logic cell. The process involves layout-based structure generation based on technology description files, transient device simulation, and parameter extraction of timing delays and power consumption. Different sources of global and local variability can be added to investigate the sensitivity of timing and power parameters. The entire process is quick and fully automated from GDSII file to PPA characteristics, and is thus suitable for use by cell and circuit designers. The extracted parameters and statistics can be directly used in high-level descriptions of digital circuits and systems.