Power-gating is the most promising run-time technique in order to reduce leakage currents in sub-100nm CMOS devices but its application is associated with numerous problems. Overhead costs in terms of additional state transition costs occur, the targeted circuit is slowed down while being in the active state, additional interfacing circuits are necessary, and in general the total impact of the power-gating technique is hard to predict at early design stages.
The goal of this thesis is to develop power-gating models for functional units at RT-level to enable
design tradeoffs and to optimize the high-level synthesis for the use of this design technique.
Main contributions of this work are 1) fast and accurate power-gating models for an estimation of the functional unit’s energy demand during the static active and sleep state as well as during a state transition, 2) optimized scheduling, binding, and allocation approaches that are able to increase the profitability of a cycle-wise power-gating and to expand the design-space exploration, and 3) a consistent design flow of the high-level synthesis decisions to subsequent design tools.
In this thesis, such an estimation and optimization framework is proposed. The models are characterized
by circuit-level simulations and have been evaluated to lead to maximum errors of 15.7% at a standard
deviation of 3.41%. They are used to estimate the energy reduction of functional RT-level components
to be 46% in average. The optimized synthesis approaches can even further reduce the remaining energy demand by up to 43% at an average reduction of 19.8%.