Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card
Catalin Bogdan Ciobanu, Francesco Conti, Cairo Caplan, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Davide Schiavone, Dominik Baumann, Alexandru Pușcașu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, Jörg Walter, Frank Oppenheimer, Gianvito Urgese, Teodoro Urso, Reoberto Bosio, Alessio Burrello, George Suciu, Mari-Anais Sachian, Nicoleta Capbun, Robert Florescu, Simona Costinescu, Ambily Suresh, Florian Lorber, Honorius Galmeanu, Mihai Munteanu, Szilard Hegedus, Darshak Sheladiya, Florian Krebs, Henrik Theiling, Mattia Paladino, Daniele Gregori, Federico Proverbio, Jan Kastil, Alexander Schober, Rainer Buchty, Mladen Berekovic, Amrit Sharma Poudel, Saleh Mulhem, Emanuele Valpreda, Andrea Zunino, Luigi Feola, Samuel Matea, Cosmin Moisa, Perian Cristian, Andrei Stan, Alexandru-Tudor Popovici, Cosmin-Andrei Popovici, George-Emil Vieriu, Daniel Gracia Pérez, Sylvain Girbal, Jérôme Quèvremont, André Sintzoff, Fatma Jebali, Caaliph Andriamisaina, Florian Egert, Maurizio Capra, Valerio Venceslai, Francesco De Maldé, Maria Elena D'Agostino, Gabriele Magnani, Davide Baroffio, Andrea Galimberti, Carlo Brandolese, Costin-Emanuel Vasile, Radu Hobincu, Alexandra-Mihaela Enescu, Calin Bira, Elijah Seth Cishugi, Marco Ottavi, Esther Soriano-Viguer, Ester Lopez-Mora, Vicente Nicolau-Gallego, Odysseas Chatzopoulos, Vasileios Karakostas, Dimitris Gizopoulos, Konstantinos Georgopoulos, Ioannis Papaefstathiou, Iakovos Mavroidis, Sallar Ahmadi-Pour, Rolf Drechsler, Jaume Abella, Sergi Alcaide, Frederik Haxel, Federico Peccia, Jonathan Schröter, Arefeh Mahdavi, Stefan Wallentowitz, Felix Mai, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Hassan Loulou, Francois Clement, Saad Saleh, Paul Detterer, Gert-Jan van Schaik, Nils Wistoff, Luca Benini, Tianhai Liu, James J. Hunt, Andreas Vörg, Philipp van Kempen, Johannes Geier, Ulf Schlic
29th Euromicro Conference Series on Digital System Design (DSD)
Sep / 2026
inproceedings
ISOLDE
Customizable Instruction Sets and Open Leveraged Designs of Embedded riscv processors
Customizable Instruction Sets and Open Leveraged Designs of Embedded riscv processors
