CMOS technology advancements have clearly helped to reduce the energy and power consumption per operation through each technology node. However, this gain in power reduction is far overcompensated by the market demand and economical necessity to increase the performance and functionality of Systems on Chip (SoC). Consequently the design community is challenged to significantly reduce the energy consumption for mobile applications, to reduce the power consumption and heat dissipation for high performance designs as well as to reduce the on-chip currents to solve reliability issues. Solutions for these challenges need to be applied during all phases of the design process and at all levels of abstraction starting from the Electronic System Level to the Layout Level. The design process has to be supported by respective EDA tools which consider the interdependence of power, energy, timing and area in order to ensure a design closure with a minimal number of design iterations. The presentation will discuss several techniques for power optimization at different levels. EDA solutions will be presented supporting the designer in analyzing and optimizing SoCs for low power. Several of these techniques and their efficiency will be demonstrated based on a case study.