Generation of Binary Patterns with Given Spatiotemporal Correlations

BIB
Radetzki, Martin and Timmermann, Bernd and Rabe, Dirk and Nebel, Wolfgang
Consideration of signal correlations and the choice of input patterns have a significant impact on the results of power estimation for digital CMOS circuits. The pattern analysis and generation method presented in this paper provides a link between probabilistic and explicit simulation techniques. Analysing sample data yields a set of signal probabilities and spatio-temporal correlations. Vice versa, binary pattern sequences can be generated meeting given statistical properties. Furthermore, the tool may be utilized to reduce the amount of stimuli to be applied in explicit simulation while maintaining the properties which are relevant to power dissipation.
01 / 1996
inproceedings
AdV
JESSI
Verlustleistungsanalyse integrierter Schaltungen (Sorry - only available in german!)
POSEIDON
Power Optimization and Simulation.Efficient strategies in deep sub-micron CMOS