NEEDS Nanoelectronic design for 3D systems


3D integration of nanoelectronic systems by stacking of bare chips allows to realize many functions compact and energy efficient. The BMBF project NEEDS (grant no. 01 M 3090)  provides a consistent basis of 3D design flows with appropriate analysis, exploration and synthesis methods and allows for the first time a joint analysis and optimization of important cost and performance factors (e.g. energy consumption, costs, testability).

OFFIS researches within the NEEDS framework thermal models for 3D chips, which are the basis for a thermal simulation of the system. Together with the simulation based activity of the system a thermal analysis can be carried out and the system will be evaluated in terms of thermal aspects. NEEDS explores key aspects of 3D design as floorplaning, networks-on-chip, thermal analysis, and testability, which enable a comprehensive knowledge base of the 3D design space exploration. To enable the 3D design space exploration necessary for a holistic simulation of the system, OFFIS creates in cooperation with the partner Fraunhofer EAS a coupling of simulators for analog and digital components of the system. Methods for 3D integration are presented with a demonstrator. The acquired design expertise is then prepared for industrial use, to allow a widespread use of stacked chips in new products in 5-10 years.

NEEDS - Nanoelektronik-Entwurf für 3D-Systeme

Hylla, Kai and Metzdorf, Malte and Grünewald, Armin and Hahn, Kai and Heinig, Andy and Knöchel, Uwe and Wolf, Susann and Miller, Felix and Wild, Thomas and Quiring, Artur and Olbrich, Markus and Sattler, Sebastian and Treytnar, Dieter; 009 / 2012

Funktional-thermische Simulation von 3D-Systemen

Metzdorf, Malte and Nebel, Wolfgang; Zuverlässigkeit und Entwurf (ZuE); 09 / 2013

Edacentrum GmbH
TU München, Fakultät für Informatik, Lehrstuhl IV: Software & Systems Engineering
Friedrich-Alexander-Universität Erlangen-Nürnberg - Lehrstuhl für Elektrische Energiesysteme
Gottfried Wilhelm Leibniz Universität Hannover
Universität Siegen
Fraunhofer-Institut für Integrierte Schaltungen IIS Institutsteil Entwurfsautomatisierung EAS


Start: 30.11.2010
End: 30.11.2013