FiPS Developing Hardware and Design Methodologies for Heterogeneous Low Power Field Programmable Servers


The FiPS project thus proposes to build a new heterogeneous super-computer class. It combines traditional high performance processors for complex tasks with many of the efficient alternative processors for simple tasks.  As the total number of processors increases, these new super-computers will be slightly faster, but will at the same time substantially reduce the energy demand. FiPS will not only have an ecological impact by reducing energy demand (and thus carbon dioxide emission), but also an economic impact by cutting one of the major costs of running a super-computing center, its energy costs. Supercomputing will become cheaper and thus affordable for many other applications.



This project has received funding from the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement no 609757.


Many of today’s technical blessings, e.g. weather forecast, fuel efficient car-shapes, medical tomography analysis or even a simple Google query depend on massive computer programs that are executed on super-computing centers with thousands of computers, which consume a lot of electrical energy. With increasing super-computing demand severe economic and ecological problems arise. Already 15% of the world-wide electrical energy is used to power all the computers in use today, and this number is quickly increasing.

There are alternative kinds of computing devices such as smart-phone processors, 3D graphic chips and reconfigurable FPGA hardware (as used in DSL modems and network switches), which can provide much higher energy efficiency than traditional processors. Today, a typical super-computing program consists of a huge number of small jobs. Some of them can be run on these alternative architectures, reducing the demand and therefore the required number of traditional high-energy, high performance processors.


The drawback of building super-computers from a heterogeneous network of processors rather than a regular grid of identical processors is that heterogeneous systems are much harder to program, as the individual properties of many different components have to be considered. For instance, different processors require different programming languages, and it has to be decided, which processor type will finally run a computation job, either to get the result as fast as possible or with the lowest energy costs. And finally, all processors working on different parts of the same problem have to synchronize on their intermediate results. This is up to now only possible in a regular grid of homogeneous processors.

To solve these issues, FiPS will setup a programming methodology, in which just a single programming language is used to write the super-computing program. The final software is then analyzed and splitted into chunks by the FiPS methodology. The best processor type for each chunk of the computation is then determined and the program is automatically prepared for  these processor types, while the necessary interactions between the computation chunks is being added. Additionally, the user receives a prediction about how fast the computation and communication will be for the program, and how much energy will be consumed. Then the implementation can be updated, trying to increase performance and/or energy efficiency.

Energy efficiency of sequence alignment tools - Software and hardware perspectives

Michal Kierzynka and Lars Kosmann and Micha vor dem Berge and Stefan Krupop and Jens Hagemeyer and Rene Griessl and Meysam Peykanu and Ariel Oleksiak; Future Generation Computer Systems; 05 / 2016

Predicting Performance and Energy Efficiency for Large-Scale Parallel Applications on Highly Heterogeneous Platforms

Jörg Walter and Ralph Görgen and Wolfgang Nebel; 19th {GI/ITG/GMM} Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, {MBMV} 2016, Freiburg im Breisgau, Germany, March 1-2, 2016.; 2016

Energy-Aware Mapping and Scheduling of Large-Scale Macro Data-Flow Applications

Walter, Jörg and Nebel, Wolfgang; 1st International Workshop on Investigating Dataflow in Embedded Computing Architecture; 01 / 2015

FPGA-Accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters

Griessl, René and Peykanu, Meysam and Hagemeyer, Jens and Porrmann, Mario and Krupop, Stefan and vor dem Berge, Micha and Kosmann, Lars and Knocke, Patrick and Kierzynka, Micha{\l} and Oleksiak, Ariel; Workshop on Heterogeneous High-performance Reconfigurable Computing; 11 / 2015

Using early power and timing estimations of massively heterogeneous computation platforms to create optimized HPC applications

Patrick Knocke and Ralph Görgen and Jörg Walter and Domenik Helms and Wolfgang Nebel; Proceedings of 2014 International Conference on Embedded and Ubiquitous Computing - EUC 2014; 08 / 2014

Christmann GmbH
Universität Bielefeld
Poznań Supercomputing and Networking Center
SOFiSTiK Hellas S.A.
National University of Ireland, Galway


Start: 31.08.2013
End: 30.08.2016

Website of project

Founding Source


GA: 609757

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