VHDL Power Simulator

Kruse, Lars and Rabe, Dirk and Nebel, Wolfgang
Power consumption of integrated circuits becomes more and more an important issue in the design phase. In this paper a new application of VHDL for gate-level power analysis and accurate timing verification is presented. Our VHDL Power Simulator (VPS) is able to accu-rately estimate the mean power consumption of a static CMOS standard cell design described in VHDL at gate-level. Additionally VPS increases the timing accuracy of logic level simulation in case of glitches, defined here as pairs of incomplete transitions. This is achieved by modifying the VHDL event handling and propagating ramps instead of infinite slope events. Our tool, implemented as an add-on to Cadence's Leapfrog VHDL simulator
01 / 1997
CHDL 1997, Hardware Description Languages and teier Applications, Toledo / Spain
EURopean Intellectual Property In Design Electronic Systems
Verlustleistungsanalyse integrierter Schaltungen(Sorry - only available in german!)
Power Optimization and Simulation.Efficient strategies in deep sub-micron CMOS

OFFIS Autoren