High level power estimation requires consideration of high level power models of IP modules. Key requirements of these modells are flexibility in size parameters, such as bitwidths. To meet this requirement many modeling approaches rely on functions that relate the design complexity to the macro size parameters [Landman,Jochens,Bogliolo]. These functions had to be deduced by careful manual analysis of the internal macro structure. In this paper we present a methodology to generate exact complexity functions automatically. Our approach is based on a special form of nonlinear regression. Increasing the performance and accuracy of high level interconnect power estimation is another important topic for high level power estimation. A fast methodology is presented in this paper which is based on switching activity of nets and provides good visualation and evaluation features. This methodology is based on a Simulated Annealing approach with an extended Minimum Span Tree algorithm.
03 / 2002
3. Kolloqium des Schwerpunktprogramms der Deutschen Forschungsgemeinschaft, TU Chemnitz
Power Reduction for Digital Audio Signal Processing (DFG Project of the University of Oldenburg)