Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim
Proceedings of the Embedded Real Time Software and Systems Congress (ERTS²) 2014
The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. In this paper, a combination of simulative method with a performance analysis based on model-checking is proposed.
The simulative approach is used for functional validation of the Synchronous Data Flow Application (SDFA) implementation and its mapping on the targeted hardware platform. In our proposed methodology, we are using a binary-compatible and cycle-accurate virtual platform representation to simulate and map all relevant architectural properties to our analytical performance model. In combination, the model-checking based method allows to guarantee timing bounds of multiple Synchronous Data Flow Application (SDFA) implementations. This approach utilizes Timed Automata (TA) as a common semantic model to represent WCET of software components (SDF actors) and access protocols including timing of shared buses, shared DMAs, private local and shared memories of the multicore platform. The resulting network of TA is analyzed using the UPPAAL model-checker for providing safe timing bounds of the implementation.
We demonstrate our approach using a multi-phase electric motor control algorithm (modeled as SDFA) mapped to Infineon's TriCore-based Aurix multicore hardware platform.
2 / 2014
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