Connecting a Company’s Verification Methodology to Standard Concepts of UVM

Frank Poppen, Marco Trunzer, Jan-Hendrik Oetjens
Proceedings of DVCon Europe 2014
Over the last decades, intelligent electronics in heterogeneous systems improved all aspects of everyone’s daily life. An advantage a modern civilization cannot ignore. The increasing complexity of the electronic components though, makes us dependent on solving a growing design verification challenge. Especially knowing, that safety relevant functionality as in automotive driving is part of this development. Standardized as well as proprietary concepts, languages and tools line up for the task [6]. Unfortunately, there is no such thing as one size fits all in this. Verification engineers need to choose and combine what fits best for the company, the design-team and application domain. They create company’s verification strategies with deep roots into the design process. Changes to the strategy need to be done carefully and incrementally to ensure continued productivity.Based on VHDL in the past, our IFS verification methodology was also implemented in SystemC (SC) [2] and covers Analog Mixed-Signal (AMS) [1] [4], and Matlab/Simulink [3] today. In this work we proceed with concepts of UVM [9] and show how UVM components are instantiable in our SC test environment to verify designs specified in VHDL (-AMS), SystemC (-AMS), Verilog (-AMS) or any language a mixed-language simulation environment exists for. Our work does not depend on proprietary technology, but is applicable to any SC based environment.
10 / 2014
Accellera Systems Initiative
Effiziente Fehlereffektsimulation mit virtuellen Prototypen zur Qualifikation intelligenter Motion-Control-Systeme in der Industrieautomatisierung (sorry - only available in german)