24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'14)
Power dissipation is one of the key parameters when designing digital circuits. While an ASIC can be exactly fitted to the requirements, targeting an FPGA means to select one of many commercially available FPGAs having different power characteristics.
In this work an approach for scaling existing power values from one FPGA implementation to other FPGAs is presented. This enables a fast design space exploration of many different FPGA target architectures. The methodology is based on characterising the most important properties of each relevant FPGA type using some test designs. Afterwards, a modelling process is started for each aspect of power dissipation. The model is evaluated using a secure hashing algorithm and a Viterbi codec as benchmark designs. The mean absolute relative error for the total dynamic power dissipation is 7.3% while static power can be modeled nearly perfectly with a mean error below 0.01%.
The methodology can be used to choose the most power-efficient target FPGA for an existing design without executing the traditional power estimation flow for every device under consideration.
10 / 2014
Methodik zum Entwurf von energiesparenden, verifizierten Systemen