A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction

Schulz, Arne and Schallenberg, Andreas and Helms, Domenik and Schulte, Milan and Reimer, Axel and Nebel, Wolfgang
Tagungsband: Integrated Circuit and System Design
Early power estimation in current designflows becomes more important nowadays. To meet this need, power estimation even on the algorithmic level has become an important step in the typical design flow. This helps the designer to choose the right algorithm right from the start and much optimisation potential can be used due to the focus on the crucial parts. In particular, algorithms for digital signal processing as applied in mobile communication systems are very power sensitive. Such algorithms massively contain multiplications with constants on parts of digital filters. In this paper we propose on the one hand our new decomposition algorithm for (nearly) optimal synthesis of constant coe_cient multipliers which we use for the evaluation of our new power model. On the other hand we propose a new power model based on the canonical signed digit (CSD) approach which can be used very fast and where the deviation of the power compared to the time consuming decomposition is 4.9 %.
09 / 2005
Architecture for Automatic Power Minimization of Signalprocessing Systems
Power Reduction for Digital Audio Signal Processing (DFG Project of the University of Oldenburg)

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