ISOLDE Customizable Instruction Sets and Open Leveraged Designs of Embedded riscv processors

Motivation

The KDT-JU programme aims to support the digital transformation of all economic and societal sectors, and speed up the transition towards a green, climate neutral and digital Europe. This transformation includes the development of new semiconductor components, such as processors, as these are considered of key importance in retaining technological and digital sovereignty and build on significant prior EC investment in knowledge generation in this domain.

Goal

ISOLDE is a KDT-JU-funded project with a duration of three years starting on May 1st 2023. The goal of ISOLDE project is to create, expand, and industrialize a European high-performance RISC-V open-source ecosystem to reduce dependence on non-EU technology suppliers and to strengthen competitive domestic microelectronics production. The targeted application area of ISOLDE is embedded systems that require significant computing power due to future functional requirements, while still being able to be part of safety-critical systems. Therefore, support for safety and security technologies is also part of the objective.

Technologies

In this context, OFFIS cooperates with 38 other European partners and contributes to the safety and security part of the ISOLDE project, known as Safety Island. OFFIS develops an open-source, generic, and configurable contract-based timing monitoring co-processor. This co-processor monitors the safety/security related system behaviours at runtime, collected by the infrastructure of the Safety Island, to guarantee the correct execution of these behaviours. Furthermore, OFFIS provides a compiler for initialization of the co-processor and configuration of the monitoring specifications. Finally, the results will be integrated with the other partners‘ components and presented in an automotive demonstrator.

 

Project management

edacentrum GmbH

Persons

External Leader

Infineon Technologies AG
Publications
Timing-Monitor co-processor in safety infrastructure

Mehlhop, Sven and Oppenheimer, Frank and Walter, Jörg; edaBarCamp; 009 / 2024

An Open-Source Safety Monitor Co-Processor for RISC-V Leveraging Contract-Based Design and Configurable Monitors

Frank Oppenheimer, Jörg Walter, Sven Mehlhop; edaWorkshop 25; Mai / 2025

Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure

Mehlhop, Sven and Walter, Jörg and Oppenheimer, Frank; 2025 Forum on Specification & Design Languages (FDL); 2025

Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card

Catalin Bogdan Ciobanu, Francesco Conti, Cairo Caplan, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Davide Schiavone, Dominik Baumann, Alexandru Pușcașu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, Jörg Walter, Frank Oppenheimer, Gianvito Urgese, Teodoro Urso, Reoberto Bosio, Alessio Burrello, George Suciu, Mari-Anais Sachian, Nicoleta Capbun, Robert Florescu, Simona Costinescu, Ambily Suresh, Florian Lorber, Honorius Galmeanu, Mihai Munteanu, Szilard Hegedus, Darshak Sheladiya, Florian Krebs, Henrik Theiling, Mattia Paladino, Daniele Gregori, Federico Proverbio, Jan Kastil, Alexander Schober, Rainer Buchty, Mladen Berekovic, Amrit Sharma Poudel, Saleh Mulhem, Emanuele Valpreda, Andrea Zunino, Luigi Feola, Samuel Matea, Cosmin Moisa, Perian Cristian, Andrei Stan, Alexandru-Tudor Popovici, Cosmin-Andrei Popovici, George-Emil Vieriu, Daniel Gracia Pérez, Sylvain Girbal, Jérôme Quèvremont, André Sintzoff, Fatma Jebali, Caaliph Andriamisaina, Florian Egert, Maurizio Capra, Valerio Venceslai, Francesco De Maldé, Maria Elena D'Agostino, Gabriele Magnani, Davide Baroffio, Andrea Galimberti, Carlo Brandolese, Costin-Emanuel Vasile, Radu Hobincu, Alexandra-Mihaela Enescu, Calin Bira, Elijah Seth Cishugi, Marco Ottavi, Esther Soriano-Viguer, Ester Lopez-Mora, Vicente Nicolau-Gallego, Odysseas Chatzopoulos, Vasileios Karakostas, Dimitris Gizopoulos, Konstantinos Georgopoulos, Ioannis Papaefstathiou, Iakovos Mavroidis, Sallar Ahmadi-Pour, Rolf Drechsler, Jaume Abella, Sergi Alcaide, Frederik Haxel, Federico Peccia, Jonathan Schröter, Arefeh Mahdavi, Stefan Wallentowitz, Felix Mai, Angelo Garofalo, Davide Rossi, Giuseppe Tagliavini, Hassan Loulou, Francois Clement, Saad Saleh, Paul Detterer, Gert-Jan van Schaik, Nils Wistoff, Luca Benini, Tianhai Liu, James J. Hunt, Andreas Vörg, Philipp van Kempen, Johannes Geier, Ulf Schlic; 29th Euromicro Conference Series on Digital System Design (DSD); Sep / 2026

TRISTAN & ISOLDE Chips-JU RISC-V Projects

Cătălin Bogdan Ciobanu, Holger Schmidt, Wolfgang Ecker, Rob Wullems, Patrick Pype, Tiberio Fanti, Dominik Baumann, Alexandru Pușcașu, Mihai Gologanu, Răzvan Stancu, Octavian Buiu, Sven Mehlhop, Jörg Walter, Gianvito Urgese, Michelangelo Barocci, Tommaso Terzano, Guido Masera, Maurizio Martina, George Suciu, Mari-Anais Sachian, Nicoleta Capbun, Alexandru Șneapotă, Călin Zamfir, Anca Burlacu-Zane, Simona Costinescu, Ambily Suresh, Diego Gigena-Ivanovich, Honorius Gâlmeanu, Mihai Munteanu, Alexandru Drîmbărean, Darshak Sheladiya, Jan Reinhard, Florian Krebs, David Engraf, Holger Blasum, Mattia Paladino, Daniele Gregori, Federico Proverbio, Jan Kastil, Pavel Zaykov, Alexander Schober, Rainer Buchty, Mladen Berekovic, Amrit Sharma Poudel, Lukas Groth, Saleh Mulhem, Emanuele Valpreda, Andrea Zunino, Luigi Feola, Samuel Matea, Cosmin Moisa, Andrei Stan, Alexandru-Tudor Popovici, George-Iulian Uleru, Cristian-Tiberius Axinte, Cosmin-Andrei Popovici, Daniel Gracia Pérez, Sylvain Girbal, Jérôme Quévremont, André Sintzoff, Angelo Garofalo, Alessandro Nadalini, Fatma Jebali, Caaliph Andriamisaina, Florian Egert, Maurizio Capra, Alessandro Aimar, Valerio Venceslai, Francesco De Maldé, Maria Elena D'Agostino, Gabriele Magnani, Davide Baroffio, Andrea Galimberti, Carlo Brandolese, Giancarlo Storti Gajani, Costin-Emanuel Vasile, Vlad-Gabriel Serbu, Alexandra-Mihaela Enescu, Radu Hobincu, Calin Bira, Elijah Seth Cishugi, Marco Ottavi; International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS); July / 2025

Partners
ACP Advanced Circuit Pursuit AG
www.newacp.ch
Barcelona Supercomputing Center
www.bsc.es
BEIA Consult International
www.beia.eu
Brno University of Technology
www.fit.vut.cz
Bytefabrik.AI GmbH
www.bytefabrik.ai
Codasip s.r.o.
www.codasip.com
Consolinno Energy GmbH
www.consolinno.de
Continental Automotive Romania
www.continental-automotive.com
E4 Computer Engineering SPA
www.e4company.com/en/
ETH Zürich
www.ethz.ch
Fent Innovative Software Solutions, S.L.
www.fentiss.com
Frontgrade Gaisler AB
www.caes.com/gaisler
FZI Forschungszentrum Informatik
www.fzi.de
Hochschule München
www.hm.edu
Infineon Technologies AG
www.infineon.com
Intel Deutschland GmbH
www.intel.de
Leonardo S.p.A.
www.leonardo.com/en/home
National Institute for R&D in Microtechnologies
www.imt.ro
National University of Science and Technology Politehnica Bucharest
www.upb.ro/en/
NXP Semiconductors Austria GmbH & Co KG
www.nxp.com
NXP Semiconductors Czech Republic s.r.o.
www.nxp.com
NXP Semiconductors Romania
www.nxp.com
Politecnico di Milano
www.elet.polimi.it/index.jsp
Politecnico di Torino
www.polito.it
Rapita Systems SL
www.rapitasystems.com
Silicon Austria Labs
www.silicon-austria-labs.com
SILVACO FRANCE
www.silvaco.com
SYSGO GmbH
www.sysgo.com
Technical University of Iasi
www.tuiasi.ro/?lang=en
Thales Alenia Space Italia S.p.A.
www.thalesgroup.com/en/global/activities/space
Thales DIS France SAS
www.thalesgroup.com
Thales Research & Technology
www.thalesgroup.com
Universitat Politècnica de València
www.upv.es/en
Universität zu Lübeck
www.iti.uni-luebeck.de
University of Bologna
www.unibo.it
ISOLDE

Duration

Start: 01.05.2023
End: 31.10.2026

Website of project

Source of funding

Key Digital Technologies Joint Undertaking, Funding reference number: KDT 101112274

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