@inproceedingsFra2017, Author = {Frank Poppen, Ralph Görgen, Kai Schulz, Andreas Mauderer, Jan-Hendrik Oetjens, Joachim Gerlach},Title = {Using an Enhanced Verification Methodology for Back-to-Back RTL/TLM Simulation},Year = {2017},Booktitle = {Proceedings of DVCon Europe 2017},type = {inproceedings},Abstract = {Critical electronic systems as in the automotive domain have to comply with the functional safety norm ISO 26262 and make extensive verification in the development process mandatory. Still, their success as a product and the return on investment are at risk if the time to market window should be missed. With test and verification consuming main effort in the development process, hardware/software co-design through application of virtual prototypes is an option to parallelize development tasks and shorten time to market significantly. Virtual prototypes can contain heterogeneous components potentially implemented at different levels of abstraction to support earliest concept evaluation and software development without the target hardware platform available. Achieving virtual prototype integration across mixed levels of abstraction is a challenge though, which is addressed in this work. We introduce a register-transfer abstraction level verification method and how it is enhanced by a technique for the simulation of transaction-level models in order to enable the mixed-level simulation of hardware and software systems and evaluate it in a Back-to-Back verification scenario.} @COMMENTBibtex file generated on