The timing analysis of hard real-time applications running on Multi-Processor System-on-Chip (MPSoC) platforms is much more challenging compared to traditional single processor. This comes from the large number of shared processing, communication and memory resources available in today’s MPSoCs. Yet, this is an indispensable challenge for enabling their usage with hard-real time systems in safety critical application domains (e.g. avionics, automotive). In this thesis, a state-based real-time analysis methodology for Synchronous Data Flow (SDF) oriented applications running on MPSoCs is proposed. This approach utilizes Timed Automata (TA) as a common semantic model to represent execution time boundaries (best-case and worst-case execution times) of SDF actors and communication FIFOs and their mapping as well as their utilization of MPSoC resources, including the scheduling of SDFGs and shared communication resource access protocols for interconnects, local and shared memories. The resulting network of TA is analyzed using the UPPAAL model-checker for obtaining safe timing bounds of the chosen implementation.