@articleDom2017, Author = {Domenik Helms ; Reef Eilers ; Malte Metzdorf ; Wolfgang Nebel}, Title = {Leakage models for high level power estimation}, Journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, Year = {2017}, Pages = {13}, Month = {11}, Url = {http://ieeexplore.ieee.org/document/8060576/}, type = {article}, Abstract = {Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow (transistor level such as BSIM), or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16nm LP) - 6.8% (for 65nm bulk) deviation over a wide range of operating conditions and process variation settings.} @COMMENTBibtex file generated on