Leakage Models for High Level Power Estimation - Dissertation zur Erlangung des Grades eines Doktors der Naturwissenschaften

BIB
Helms, Domenik
Leakage currents are one major concern when designing sub-100nm CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimisation requires early leakage prediction, and for electronic system level design, this means estimation capabilities at RT level or above. Existing models either offer very accurate, but also very slow simulation at transistor level (such as BSIM or PSP), or faster modelling at gate level, disregarding relevant parameters (such as the Liberty library). The goal of this thesis is to develop RT level leakage macro models, being even faster than recent gate level models, while regarding all relevant parameters and thus being just slightly less accurate than transistor level models. The main contributions of this work are • A powerful, yet fast single transistor leakage model, which can be characterised using industrial standard models. • To cope with the complexity, this model is abstracted in layers, first towards gate models, then RT hard macros, and finally RT soft macros, while explicitly or implicitly preserving parameter influences. • All relevant parameters (such as varying process parameters or temperature) are forwarded through all abstraction layers and can still be explicitly regarded at system level. In this thesis, such a respective estimation framework is proposed, describing the subthreshold, gate, and junction leakage of industrial 90nm, 65nm, and 45nm devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described; as an example of use, channel length, oxide thickness and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behaviour of an entire family of RT components. Compared to SPICE/BSIM, a model prediction is computed up to a million times faster for large RT components, and is within 3.6% - 6.9% standard deviation (depending on the analysed technology) over a wide range of operating conditions and process variation settings.
11 / 2009
phdthesis
CLEAN
Controlling LEAkage power in NanoCMOS SoCs