Dr. Ing. Maher Fakih Senior Researcher und Zertifizierter Projektmanager (GPM - Level C)

Dr. Ing. Maher Fakih
Kontaktdaten
Tätigkeiten

Position im OFFIS

Senior Researcher und Zertifizierter Projektmanager (GPM - Level C)

Forschungsbereiche

Verkehr / Hardware/Software-Entwurfsmethodik

Competence Cluster

Embedded Systems Design (ESD), Multi-Scale Multi-Rate Simulation (MS²)

Position an der Uni

Lecturer
Biografie
Maher Fakih received his M.Sc. in computer science in 2011 and his Ph.D. degree in 2016 from the Carl von Ossietzky University of Oldenburg, Germany.
He is currently working as a senior researcher in the Group "Hardware/Software Design Methodology" at OFFIS Institute for Information Technology. He is also a partial Lecturer at the Carl von Ossietzky University of Oldenburg.
Dr. Fakih is also a Technical Program Committe Member of MBMV, FDL and HIP3ES workshops and contributes as a reviewer of scientific publications of several international conferences/workshops (DATE, IDEA, DCIS, ESLsyn, ReCoSoC, ...).

His research interest lies in: Electronic System-Level Design and Automation, Design Methodologies, Virtual-prototyping and Real-time Analysis methods. He is currently focusing on developing Real-time and Power analysis methods of Dataflow applications running on MPSoCs (multiprocessor system-on-chip) with shared resources.

Maher Fakih contributed to several EU projects including COMPLEX (Codesign and power Management in Platform-based design space Exploration) and MOTORBRAIN. Currently, he is OFFIS internal Projectmanager of the SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) EU project.

Maher Fakih is a Certified Project Management Associate according to IPMA Level D.
News

+49 441 9722-287

Maher.Fakih(at)offis.de

O25

OFFIS - Institut für Informatik
Escherweg 2
26121 Oldenburg

Publikationen
von Dr. Ing. Maher Fakih

2020

Capturing Neural-Networks as Synchronous Dataflow Graphs

Daniel Lünemann and Maher Fakih and Kim Grüttner; Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) 2020; 2020

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Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs

Razi Seyyedi, Sören Schreiner, Maher Fakih, Kim Grüttner and Wolfgang Nebel; Microprocessors and Microsystems; 2020

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2019

A Design-flow for implementing, validating and evaluating Machine-learning Classifiers on FPGAs

Jan Cordes and Maher Fakih; International Conference on Omni-layer Intelligent systems (COINS); 2019

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Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Patricia Balbastre, Mikel Azkarate-askatsua, Peio Onaindia, Poggi Tomaso, Alina Lenz, Roman Obermaisser, Adele Maleki, Yosab Bebawy, Duncan Graham, Nera González Romero, Elena Quesada Gonzalez, Johnny Öberg, Tage Mohammadat, Timmy Sundström, Salvador Peiró Frasquet; Journal of Low Power Electronics and Applications; 2019

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Experimental Evaluation of Scenario Aware Synchronous Data Flow Based Power Management

Oliver Klemp and Maher Fakih and Kim Grüttner and Ralf Stemmer and Wolfgang Nebel; International Conference on Omni-layer Intelligent systems (COINS); 2019

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Feasibility Study of Probabilistic Timing Analysis Methods for SDF Applications on Multi-Core Processors

Ralf Stemmer and Hai-Dang Vu and Maher Fakih and Kim Grüttner and Sebastien Le Nours and Sebastien Pillement; Mar / 2019

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Implementation of Time-Triggered MPSoCs with support for tool-based system generation on FPGAs

Jan-Henrik Bruhn and Kim Grüttner and Maher Fakih and Wolfgang Nebel; 4th International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS); 01 / 2019

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Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Henning Schlender and Maher Fakih and Kim Grüttner and Wolfgang Nebel ; 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE); 3 / 2019

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SAFEPOWER: Application of Power Management Techniques in SoCs for Safety-Relevant Systems

Kim Grüttner and Maher Fakih and Mikel Azkarate-Askasua and Peio Onaindia and Roman Obermaisser; International Conference on Omni-layer Intelligent systems (COINS); 2019

BIB

2018

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

Peio Onaindia and Tomaso Poggi and Mikel Azkarate-askatsua and Kim Grüttner and Maher Fakih and Salvador Peiro and Patricia Balbastre; Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29 – 31, 2018 ; 2018

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Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs using GALI

Razi Seyyedi and Sören Schreiner and Maher Fakih and Kim Grüttner and Wolfgang Nebel; Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29 – 31, 2018; 2018

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Towards Power Management Verification of Time-Triggered Systems using Virtual Platforms

Sören Schreiner and Razi Seyyedi and Maher Fakih and Kim Grüttner and Wolfgang Nebel; International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) XVIII, Samos Island, Greece, July 15-19, 2018; 7 / 2018

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2017

A functional Test Framework to observe MPSoC Power Management Techniques in Virtual Platforms

Sören Schreiner and Maher Fakih and Kim Grüttner and Wolfgang Nebel and Duncan Graham and Salvador Peiro Frasquet; 20th Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - September 1, 2017; 2017

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Automatic SDF-based Code Generation from Simulink Models for Embedded Software Development

Maher Fakih and Sebastian Warsitz; HIP3ES 2017 ; 1 / 2017

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Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs

Christof Schlaak and Maher Fakih and Ralf Stemmer; HIP3ES 2017; 1 / 2017

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SAFEPOWER project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Maher Fakih, Alina Lenz, Mikel Azkarate-Askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser, Adele Maleki, Johnny Öberg, Mohamed Tagelsir Mohammadat, Jon Pérez-Cerrolaza, Ingo Sander, Ingemar Söderquist; Microprocessors and Microsystems; May / 2017

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Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO); 1 / 2017

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Towards Timing and Power Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Maher Fakih; MBMV 2017; 2 / 2017

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Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs

Razi Seyyedi, M. T. Mohammadat, Maher Fakih, Kim Grüttner, Johnny Öberg and Duncan Graham; 12th IEEE International Symposium on Industrial Embedded Systems (SIES); 6 / 2017

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2016

Simulink-Modell-Übersetzung in synchrone Datenflussgraphen

Sebastian Warsitz and Maher Fakih; Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'2016); 3 / 2016

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State-Based Real-Time Analysis of Synchronous Data-flow (SDF) Applications on MPSoCs with Shared Communication Resources

Maher Fakih; 7 / 2016

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Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel; Integrating Dataflow, Embedded computing and Architecture (IDEA'2016); 4 / 2016

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2015

State-Based Real-Time Analysis of SDF Applications on MPSoCs with Shared Communication Resources

Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg; Journal of Systems Architecture (JSA): the EUROMICRO Journal; oct / 2015

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State-Based Real-Time Analysis of SDF Applications on Multi-Cores

Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg; 1st International Workshop on Investigating Dataflow in Embedded computing Architecture (IDEA); 1 / 2015

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2014

Hardware-Based Real-Time Simulation on the Raspberry Pi - Hardware prototypes are commonly used during embedded control unit design. Existing commercial tools offer an integrated workflow from mathematical models down to hardware simulation. Researchers a

Walter, Jörg and Fakih, Maher and Grüttner, Kim; 01 / 2014

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MOTORBRAIN: MODEL-BASED DESIGN AND VIRTUAL INTEGRATION OF AN INTELLIGENT AND SAFE ELECTRICAL POWERTRAIN

Sven Rosinger, Maher Fakih and Jörg Walter; 3 / 2014

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Multicore Performance analysis of a Multi-phase Electrical Motor Controller

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim; Proceedings of the Embedded Real Time Software and Systems Congress (ERTS²) 2014; 2 / 2014

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2013

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Maher Fakih, Kim Grüttner, Martin Fränzle, and Achim Rettberg; International Embedded Systems Symposium (IESS); 6 / 2013

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Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim; Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013; 03 / 2013

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2012

Virtual-Platform in the Loop Simulation for Accurate Timing Analysis of Embedded Software on Multicore Platforms

Fakih, Maher and Grüttner, Kim; ASIM-Treffen der Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation; 2 / 2012

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2011

Non-intrusive TLM-2.0 Transaction Observation, Interception, and Augmentation

Hartmann, Philipp A. and Fakih, Maher A. and Grüttner, Kim; 09 / 2011

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Simulink and Virtual Hardware Platform Co-Simulation for Accurate Timing Analysis of Embedded Control Software

Fakih, Maher A. and Poppen, Frank and Grüttner, Kim, Rettberg, Achim; ASIM-Konferenz STS/GMMS 2011; 02 / 2011

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Projekte
von Dr. Ing. Maher Fakih

G

GENIAL!

Gemeinsame Elektronik Roadmap für Innovationen der Automobilen Wertschöpfungskette!

Laufzeit: 2018 - 2023