Dr. rer. nat. Domenik Helms Wissenschaftlicher Mitarbeiter

Dr. rer. nat. Domenik Helms
Kontaktdaten
Tätigkeiten

Position im OFFIS

Wissenschaftlicher Mitarbeiter

Forschungsbereiche

Verkehr / Hardware/Software-Entwurfsmethodik

Competence Cluster

Embedded Systems Design (ESD)

News

+49 441 9722-429

Domenik.Helms(at)offis.de

OFFIS - Institut für Informatik
Escherweg 2
26121 Oldenburg

Publikationen
von Dr. rer. nat. Domenik Helms

2021

A Measurement-based Performance Evaluation Framework for Neural Networks on MPSoCs

Quentin Dariol, Sebastien Le Nours, Sebastien Pillement, Ralf Stemmer, Kim Grüttner, Domenik Helms; 15ème Colloque National du GDR SOC2; Jun / 2021

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2020

An Embedded CNN Implementation for On-Device ECG Analysis

Alwyn Burger, Chao Qian, Gregor Schiele, Domenik Helms; 2020 IEEE International Conference on Pervasive Computing and Communications Workshops (PerCom Workshops); March / 2020

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Patent: LUTnet – Vorrichtung zur rechnergestützten Klassifikation von Sensordaten unter Verwendung einer trainierten neuronalen Netzstruktur (LUTnet - Device for computer-aided classification of sensor data using a trained neural network structure)

Domenik Helms, Gregor Schiele, Moritz Könnecke; 2020

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Understanding Ageing Mechanisms

Domenik Helms, Daniele Rossi, Haider Muhi Abbas, Mohd Syafiq Mispan, Shengyu Duan, Lorena Anghel, Helena-Maria Dounavi, Gaole Sai; 2020

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2018

Leakage Models for High-Level Power Estimation

Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel; IEEE Trans. on Computer-Aided Design of ICs and Systems; August / 2018

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2017

Leakage models for high level power estimation

Domenik Helms ; Reef Eilers ; Malte Metzdorf ; Wolfgang Nebel; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 11 / 2017

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TCAD-Based Characterization of Logic Cells: Power, Performance, Area, and Variability

HW. Karner, C. Kernstock, Z. Stanojevi´c, O. Baumgartner, F. Schanovsky, M. Karner, D. Helms, R. Eilers, M. Metzdorf; Proceedings of the 2017 Intl. Symp. on VLSI Technology, Systems and Application; 4 / 2017

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Timing Modeling at RT-level by Separation of Design - and Stress Related Aging Impacts

Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel; Proceedings of the 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS); 9 / 2017

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User dependent Aging Prediction Model for Automotive Controllers with Power Electronics

Sunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel; Proceedings of the 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS); 9 / 2017

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2016

Analysis of NBTI Effects on High Frequency Digital Circuits

Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel; DATE; 3 / 2016

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MoRV: Modelling Reliability under Variability

Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel, Kay-Uwe Giering, Roland Jancke, Gerhard Rzepa, Tibor Grasser, Markus Karner, Praveen Raghavan, Ben Kaczer, Dan Alexandrescu, Adrian Evans, Gunnar Rott, Peter Rotter, Hans Reisinger, Wolfgang Gustin; SELSE 12 proceedings; 3 / 2016

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RT Level Timing Model for Aging Prediction

Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel; DATE; 3 / 2016

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The Long Way Towards Design for Reliability Support

Helms, Domenik; 4 / 2016

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2015

Abstracting TCAD models above the circuit level.

Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel; March / 2015

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Facilitating Cross-Layer Reliability Management through Universal Reliability Information Exchange

Enrico Costenaro, Domenik Helms, Nematollah Bidokhti, Adrian Evans, Maximilian Glorieux and Dan Alexandrescu; DAC - Design Automation Conference; 6 / 2015

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2014

Considering Variation and Aging in a Full Chip Design Methodology at System Level

Domenik Helms and Kim Grüttner and Reef Eilers and Malte Metzdorf and Kai Hylla and Frank Poppen and Wolfgang Nebel; Electronic System Level Synthesis Conference (ESLsyn), Proceedings of the 2014; 6 / 2014

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Considering Variation and Aging in a Full Chip Design Methodology at System Level

Domenik Helms and Kim Grüttner and Reef Eilers and Malte Metzdorf and Kai Hylla and Frank Poppen and Wolfgang Nebel; Proceedings of The 2014 Electronic System Level Synthesis Conference (ESLsyn'14), May 31- Jun 01 2014, San Francisco, CA, USA; 5 / 2014

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2013

Abstraktion des Switching-Trap-Modells für eine leistungsorientierte NBTI-Simulation

Eilers, Reef and Bergemann, Carl and Helms, Domenik and Nebel, Wolfgang; Proceedings of edaWorkshop 2013; 5 / 2013

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Closing the gap between technology and application needs

Nebel, Wolfgang and Helms, Domenik and Grüttner, Kim and Oppenheimer, Frank; 5 / 2013

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Energieeffiziente Software

Nebel, Wolfgang and Schomaker, Gunnar and Helms, Domenik; 12 / 2013

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2012

Bewertung und Optimierung der Robustheit mikroelektronischer Systeme

[Metzdorf, Malte and Helms, Domenik]; 09 / 2012

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Design methodology for a self-healing signal processing unit on the example of an FIR filter

[Metzdorf, Malte and Eilers, Reef and Helms, Domenik and Nebel, Wolfgang]; 05 / 2012

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Phase space based NBTI model

Eilers, Reef and Metzdorf, Malte and Rosinger, Sven and Helms, Domenik and Nebel, Wolfgang; 09 / 2012

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Über die Notwendigkeit neuer Modellierungskonzepte komplexer eingebetteter Systeme

Nebel, Wolfgang and Helms, Domenik and Grüttner, Kim and Oppenheimer, Frank; 05 / 2012

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2011

Robustness evaluation of embedded software systems

Lu, Weiyun and Radetzki, Martin and Metzdorf, Malte and Helms, Domenik and Nebel, Wolfgang; 05 / 2011

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2009

Hybrid Logical-Statistical Simulation with Thermal and IR-Drop Mapping for Degradation and Variation Prediction

Helms, Domenik and Hylla, Kai and Nebel,Wolfgang; 08 / 2009

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Leakage Models for High Level Power Estimation - Dissertation zur Erlangung des Grades eines Doktors der Naturwissenschaften

Helms, Domenik; 11 / 2009

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2008

A Comparison of Approaches for High-level Power Estimation of LUT-based DSP Components

Jevtic, Ruzica and Carreras, Carlos and Helms, Domenik; 2008 International Conference on ReConFigurable Computing and FPGAs; 01 / 2008

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Leakage Models for High Level Power Estimation

Helms, Domenik; 03 / 2008

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On Leakage Currents: Sources and Reduction for Transistors, Gates, Memories and Digital Systems

Nebel, Wolfgang and Helms, Domenik; 01 / 2008

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Verfahren zur Simulation elektrischer Schaltkreise

Helms, Domenik and Hoyer, Marko; 01 / 2008

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2007

Logic design techniques for 65 to 45 nm and below for reducing total energy and solving technology variations problems

Domenik Helms, Wolfgang Nebel; 14th IEEE International Conference on Electronics, Circuits and Systems; December / 2007

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Modeling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components.

Marko Hoyer, Domenik Helms, Wolfgang Nebel; Integrated Circuit and System Design; 2007

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RTL Power Modeling and Estimation of Sleep Transistor based Power Gating

Rosinger, Sven and Helms, Domenik and Nebel, Wolfgang; proceeding in PATMOS_2007; 01 / 2007

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System level optimization of static power consumption in nano CMOS circuits

Domenik Helms; 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems; June / 2007

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Voltage- and ABB-Island Optimization in High Level Synthesis

Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel; Proceedings of the 2007 International Symposium on Low Power Electronics and Design; August / 2007

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2006

Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage

; Tagungsband; 09 / 2006

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Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation

Helms, Domenik and Ehmen, Günter and Nebel, Wolfgang; Tagungsband; 10 / 2006

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Leakage Currents in Nanometer CMOS

Nebel, Wolfgang and Helms, Domenik and Keshavarzi, Ali; -; 10 / 2006

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2005

A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction

Schulz, Arne and Schallenberg, Andreas and Helms, Domenik and Schulte, Milan and Reimer, Axel and Nebel, Wolfgang; Tagungsband: Integrated Circuit and System Design; 09 / 2005

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High-Level Power Estimation and Analysis

Nebel, Wolfgang and Helms, Domenik; Low-Power Electronics Design; 01 / 2005

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Leakage Power Modeling, Estimation and Optimization

Helms, Domenik; Tagungsband für die Workshopteilnehmer; 04 / 2005

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Low Power Design Solutions

Nebel, Wolfgang; MEDEA+ Design Automation Roadmap; 07 / 2005

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2004

Leakage in CMOS Circuits - An Introduction

Helms Domenik and Schmidt, Eike and Nebel, Wolfgang; Tagungsband; 09 / 2004

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2003

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Stammermann, Ansgar; Tagungsband ICCAD; 01 / 2003

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Interconnect Driven Low Power High-Level Synthesis

Stammermann, Ansgar and Helms, Domenik and Schulte, Milan and Schulz, Arne and Nebel, Wolfgang; Tagungsband PATMOS 2003; 01 / 2003

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2002

An Improved Power Macro-Model for Arithmetic Datapath Components

Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel; PATMOS; 9 / 2002

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Low Power Design for SoCs

Nebel, Wolfgang and Helms, Domenik and Schmidt, Eike and Schulte, Milan and Stammermann, Ansgar; Tagungsband; 10 / 2002

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