@articlemah2019, Author = {Maher Fakih, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Patricia Balbastre, Mikel Azkarate-askatsua, Peio Onaindia, Poggi Tomaso, Alina Lenz, Roman Obermaisser, Adele Maleki, Yosab Bebawy, Duncan Graham, Nera González Romero, Elena Quesada Gonzalez, Johnny Öberg, Tage Mohammadat, Timmy Sundström, Salvador Peiró Frasquet}, Title = {Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems}, Journal = {Journal of Low Power Electronics and Applications}, Year = {2019}, Isbn = {2079-9268}, Booktitle = {Special Issue "Ultra-low Power Embedded Systems"}, Doi = {10.3390/jlpea9010012}, Url = {http://www.mdpi.com/2079-9268/9/1/12}, type = {article}, Abstract = {With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety critical domains like railway and avionics multi-core processors are introduced under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This paper provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most importation outcome of the project. Furthermore, the application of this reference architecture in a novel railway interlocking and flight controller avionic systems was demonstrated showing the capability to achieve power savings up to 37% while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.} @COMMENTBibtex file generated on