Low-Level Space Optimization of an IDCT/FDCT Implementation for a Bit-Serial Fully Pipelined Architecture

Weber, Raphael, Henkler, Stefan and Rettberg, Achim
To fulfill market requirements, the design of hardware architectures has to provide 1) small latencies as well as 2) accurate computable latencies on 3) strongly restricted environments. Current architectures address either requirement 1) and 3) (asynchronous architectures) or requirement 2) (synchronous architectures). Caused by their non-determinism, asynchronous architectures, in principle, can not fulfill requirement 2). The main problem of synchronous architectures is that they typically have global control units with long control wires preventing small latencies. Based on our MACT approach which provides small, computable latencies, we present an approach which optimizes the MACT architecture to address also the problem of strongly restricted environments. This is realized by merging the basic control logic of the MACT architecture to facilitate the positive effects of asynchronous and synchronous architectures. The fast and inverse discrete cosine transformation parts of the MPEG2 compression algorithm serve as an example to evaluate our optimization.
12 / 2011
SPES 2020
Software Plattform Embedded Systems 2020 (sorry - only available in German)

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