@inproceedings{Mar2007,Author = {Marko Hoyer, Domenik Helms, Wolfgang Nebel},Title = {Modeling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. },Year = {2007},Pages = {171-180},Publisher = {Springer},Series = { Lecture Notes in Computer Science (LNCS, volume 4644)},Booktitle = {Integrated Circuit and System Design},Doi = {ISBN 978-3-540-74441-2},type = {inproceedings},Abstract = {To adress the problem of static power consumption, approaches as ABB and AVS have been proposed to reduce runtime leakage in integrated circuits. Applying these techniques is a trade off between power and delay, which is best decided early in the design flow. Therefore high level power and delay estimation is needed. In our work, we present a fast RT Level delay macro model considering supply and bias voltages and temperature. Errors below 5% combined with only few characterization data enables this approach to be used by high level design tools to support leakage optimization by e.g. ABB and AVS.}}@COMMENT{Bibtex file generated on }