@inproceedings{Ral2017,Author = {Ralf Stemmer and Maher Fakih and Kim Grüttner and Wolfgang Nebel},Title = {Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication},Year = {2017},Month = {1},Booktitle = {9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)},type = {inproceedings},note = {Scenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability.On the one side, they support the timing analysis of real-time applications, es},Abstract = {Scenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability.On the one side, they support the timing analysis of real-time applications, especially those running on MPSoCs, due to the clean separation of computation and communication phases in their executing nodes.On the other side, SADFGs allow the expression of a more dynamic behaviors than Synchronous dataflow graphs by allowing dynamic token-rates of single nodesdepending on pre-defined typical scenarios. The fact which leads to more efficiency and better throughput.In this paper, we describe the extension of a previous model-checking based real-time analysis approach to allow the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multiprocessorarchitecture. We demonstrate our approach on an MPEG decoder application being viable toobtain the worst-case end-to-end latency of its implementation under different scenarios on a 2-tiles MPSoC.}}@COMMENT{Bibtex file generated on }