@article{Mah2015,
Author = {Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg},
Title = {State-Based Real-Time Analysis of SDF Applications on MPSoCs with Shared Communication Resources},

Journal = {Journal of Systems Architecture (JSA): the EUROMICRO Journal},
Year = {2015},
Publisher = {Elsevier North-Holland, Inc.},
Edition = {Volume 61 Issue 9},
Isbn = {1383-7621},
Booktitle = {Journal of Systems Architecture (JSA): the EUROMICRO Journal},
Doi = {10.1016/j.sysarc.2015.04.005},
Url = {http://dx.doi.org/10.1016/j.sysarc.2015.04.005},
type = {article},
note = {The timing predictability of Multi-Processor System on Chip (MPSoC) platforms with hard real-time applications is much more challenging than
that of traditional platforms due to their large number of shared processing, communication and memory resources.},
Abstract = {The timing predictability of Multi-Processor System on Chip (MPSoC) platforms with hard real-time applications is much more challenging than
that of traditional platforms due to their large number of shared processing, communication and memory resources. Yet, this is an indispensable
challenge for guaranteeing their safe usage in safety critical domains (avionics, automotive).
In this article, a real-time analysis based on model-checking is proposed. The model-checking based method allows guaranteeing timing
bounds of multiple Synchronous Data Flow Application (SDFA) implementations. This approach utilizes Timed Automata (TA) as a common
semantic model to represent WCET of software components (SDF actors) and shared communication resource access protocols for buses, DMA,
private local and shared memories of the MPSoC. The resulting network of TA is analyzed using the UPPAAL model-checker for providing safe
timing bounds of the implementation. Furthermore, we will show the extension of our previous system model enabling single-beat inter-processor
communication style beside the burst-transfer style and provide the implementation of the complete set of TA templates capturing the considered
system model.

We demonstrate our approach using a multi-phase electric motor control algorithm (modeled as SDFA) mapped to Infineon’s TriCore-based
Aurix multicore hardware platform with both the burst and single-beat inter-processor communication styles. Our approach shows a significant
precision improvement (up to a percentage improvement of 300%) compared with the worst-case bound calculation based on a pessimistic
analytical upper-bound delays for every shared resource access. In addition, scalability is examined to demonstrate analysis feasibility for small
parallel systems, up to 40 actors mapped to 4-tiles and up to 96 actors on a 2-tiles platforms.}
}
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