@inproceedings{Neb2001,
Author = {Nebel, Wolfgang and Poppen, Frank},
Title = {Comparison of a RT -  and Behavioral-Level Design Entry Regarding Power},

Year = {2001},
Month = {01},
Organization = {SNUG Europe 2001, March 12.-13., 2001, part A 1.3},
type = {inproceedings},
note = {SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore s Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors},
Abstract = {SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is expected to double every 18 months as Moore s Law did not loose its correctness yet. Higher levels of abstraction need to be introduced to handle the billions of transistors of future designs and to keep, or even better shorten, time to market. At the same point the designer of these sub micron devices will have to observe the power dissipation of his SoC. The continuous enhancement of battery s energy capacity does not keep up with the more and more power consuming applications. This is critical to handheld products like cellular phones and PDAs. RT level abstraction is the entry point in most designflows today. During synthesis a gate level netlist is being generated. If any, power estimations and optimizations usually are performed on these netlists. In the low power community it is well known that at this point most opportunities of higher level power optimizations are wasted. The better flow is the one with a behavioral level entry point and an early focus on power dissipation. Synopsys offers its Behavioral Compiler which introduces this higher level of abstraction. By entering the algorithms only, the designer does not need to do needlework on scheduling and binding of operations. Behavioral Compiler even offers automated gated clock insertion which should result in reduced power dissipation. As a design case, this paper introduces a bank of six fourth order IIR filters, which is implemented in VHDL code at RT level as well as behavioral level. The differences of the two specifications are explained and the dissimilar design flows are elucidated. The outcome of both flows is a gate level mapped design which is, then, analyzed in terms of power dissipation. By iterating both flows, while applying power optimizations to the VHDL and power constraints to the synthesis scripts, the synthesized gate level netlists are improved regarding power. The reader will hereby undergo the advantages and limits of each methodology.}
}
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